For configuring a demultiplexing apparatus for demultiplexing an input signal in which signals of a plurality of channels are frequency-multiplexed into individual signals and configuring a multiplexing apparatus for frequency-multiplexing signals of a plurality channels to output a multiplexed signal, the same number of filters and frequency conversion circuits as the number of channels become necessary. Thus, there is a problem in that apparatus size and adjusting parts of the apparatus increase. As a method for solving this problem, a digital signal demultiplexing apparatus and a digital signal multiplexing apparatus of collective processing type using digital signal processing circuits are used (refer to non-patent document 1, for example).
FIG. 7 is a block diagram of a digital signal demultiplexing apparatus based on the principle described in the non-patent document 1. FIG. 7 shows a configuration for demultiplexing and outputting 8 channels at the maximum, and the configuration is provided with a serial-parallel conversion circuit 71, eight subfilters 72 and an 8 point discrete Fourier transform circuit 73. The eight subfilters 72 are FIR (Finite Impulse Response) filters that are obtained by polyphase-decomposing a same original filter into eight types, and are identical in bandwidth, but are different in delay time.
First, an input signal into the digital signal demultiplexing apparatus is serial-to-parallel converted in a ratio of 1 to 8 by the serial-parallel conversion circuit 71. The sampling rate of each of the eight series output samples of the serial-parallel conversion circuit 71 is ⅛ of that of the input signal, and each of the samples is filtered by the subfilter 72 and is output. Output samples of eight series from the subfilters 72 are input to each point of the 8 point discrete Fourier transform circuit 73 so that the output samples are discrete Fourier transformed and output by eight samples.
FIG. 9 is a diagram showing signals to be processed by the digital signal demultiplexing apparatus shown in FIG. 7. The bandwidth of each channel is the same as a bandwidth of a prototype filter before polyphase-decomposed to subfilters 72, and each center frequency is provided as a frequency corresponding to each output of the 8 point discrete Fourier transform circuit 73, that is, provided as fc(i)=(Fs/8)(i−1). In this equation, fc(i) is a center frequency of channel CHi (i is an integer from 1 to 8), and Fs is a sampling frequency of an input signal to the digital signal demultiplexing apparatus.
FIG. 8 is a block diagram of a digital signal multiplexing apparatus based on the principle described in the non-patent document 1. FIG. 8 shows a configuration for multiplexing and outputting eight channels at the maximum, and the configuration is provided with a parallel-serial conversion circuit 81, eight subfilters 82 and an 8 point discrete inverse Fourier transform circuit 83. The eight subfilters 82 are the same as the 8 subfilters 72 shown in FIG. 7.
Signals from each channel are input to each point of the 8 point discrete inverse Fourier transform circuit 83 so as to be discrete inverse Fourier transformed. Each output of the 8 point discrete inverse Fourier transform circuit is filtered by the subfilter 82 so that a filtered signal is output, and further, output signals are parallel-to-serial converted in a ratio of 8 to 1 by the parallel-serial conversion circuit 81. Sampling rate at the output of the parallel-serial conversion circuit 81 is eight times that of each input signal, and the signal of the rate is output from the digital signal multiplexing apparatus. According to the above-mentioned configurations, like the digital signal demultiplexing apparatus of FIG. 7, a frequency-multiplexed signal as shown in FIG. 9 is output.
In addition, the non-patent document 2 is a document on fast Fourier transform and fast Fourier inverse transform. As is well known, fast Fourier transform and inverse transform are realized by applying butterfly computation onto an input signal repeatedly. Processing flow for this computation follows a signal flow graph as shown in pages 153-158 of the non-patent document 2. An example of a signal flow graph of fast Fourier inverse transform (8 point) is shown in FIG. 11. W(k) (k=0, −1, −2, . . . , −(N/2)+1:N is a number of points) is called a rotation factor, and is a complex number represented by the following equation.
      W    ⁡          (      k      )        =      ⅇ          j      ⁢                        2          ⁢          π          ⁢                                          ⁢          k                N            Nodes indicated by black circles represent input signals and results calculated from the input signals. These are input to next nodes according to the direction of the arrows. When a rotation factor is shown at a lower part of the arrow, a signal is multiplied by the rotation factor, and addition or subtraction between signals is carried out at a point where arrows merge.    [Non Patent document 1] F. Takahata, et. al., “A PSK Group Modem Based on Digital Signal Processing: Algorithm, Hardware Design, Implementation and Performance”, International Journal of Satellite Communications, Vol. 6, pp. 253-266, 1988    [Non Patent document 2] Bringham E. Oran, “Fast Fourier Transform”, Prentice-Hall, Inc. 1974